module lvds_tx_pack
#(
parameter  SYNC1=10'b1010_1010_10,
parameter  SYNC2=10'b1010_1010_11
)
(

input				rst,
input				clk_10M,
input				clk_100M,

input				tx_vld,
input	[9:0]		tx_data,

input				tx_done,
output			tx_out

);


wire 					tx_in;
reg					tx_vld_r=0;
reg					tx_done_r;

reg	[9:0] 		tx_dra;		// tx_data_ra
reg	[9:0] 		tx_drb;		// tx_data_rb;
reg   [9:0]       tx_dr;
reg   				tx_dr_en;

reg   [9:0]       tx_sft;    	//  tx shift  
reg   [3:0]       sft_count;



reg	[9:0]       lvds10_data_in;

reg	[1:0]       sync_data_st;
     

assign  tx_in=tx_sft[9];





always@(posedge clk_10M )
begin
tx_done_r<=tx_done;
tx_vld_r <=tx_vld;
end





always@(posedge clk_10M or posedge rst)
if(rst) begin
	lvds10_data_in 	<=SYNC1;
	 sync_data_st	   <=3'b0;
end
else case(sync_data_st)
0:begin
	lvds10_data_in	<=SYNC1;
	if(tx_vld) begin
		lvds10_data_in	<=SYNC2;
		sync_data_st		   <=3'd1;
	end
end
1:begin
		sync_data_st		  <=3'd2;
		if(tx_vld_r) begin
	   lvds10_data_in<=tx_data;
		end
end	
2:begin

		if(tx_done_r) begin
		   lvds10_data_in <=SYNC1;//idle 空闲
			sync_data_st	<=3'd0;
		end
		else begin
			lvds10_data_in<=tx_data;
		end
	
   end
default:sync_data_st		  <=3'd0;
endcase




always@(posedge clk_100M or posedge rst)
if(rst) begin
tx_dra<=0;
tx_drb<=0;
end
else begin
	tx_dra<=lvds10_data_in;
	tx_drb<=tx_dra;
	tx_dr_en<=1'b0;
	
	if(tx_dra!=tx_drb) begin  
		tx_dr<=lvds10_data_in;		
		tx_dr_en<=1'b1;
	end
	//else
	//tx_dr_en<=1'b0;
end

//if(|(tx_dra^tx_drb))


always@(posedge clk_100M or posedge rst)
if(rst) begin
 tx_sft		<=10'b1010_1010_10;
 sft_count	<=0;
 
end
else begin
	if(tx_dr_en) begin
		tx_sft<=tx_dr;
		sft_count<=0;     //shift register counter
	end
	else if(sft_count==9) begin
		tx_sft<=tx_dr;
		sft_count<=0;
	end
	else begin
		tx_sft<={tx_sft[8:0],tx_sft[9]} ;
		sft_count<=sft_count+1'b1;
	end


end



lvds_tx	lvds_tx_inst ( //phy --- physical layer
	.tx_in ( tx_in),
	.tx_out ( tx_out )
	);
endmodule
